Summary

Model the behaviour of a DDFSTRT programmed below the hardwired start
window ($18), fixing the vAmigaTS Agnus/DDF oldhwstop3/4 divergence and
most of the hwstop/single band residuals with it.

Hardware model

The DDF sequencer flop walk (transcribed from vAmiga, pinned by the
oldhwstop A500 photos) already produced the right DMA pattern for
DDFSTRT=$10: the comparator fires while SHW is still down, so a fresh
line starts no run; but OCS only clears SHW when a fetch run completes,
so the latch survives a run-less line and the NEXT line's $10 match does
arm a run - anchored at the raw $10 fetch grid, draining through the
hardware stop. Such lines fetch on alternating rasters, with the picture
sitting linearly left of the standard grid (the early words run through
the left border, kept visible by the tests' unreachable DIWSTOP h-flop
wrap).

The divergence was renderer-side: the captured run geometry was
discarded for origins below $18 ("keep the register view"), the
register-derived placement clamped sub-$18 starts to the hard start, and
the no-run lines were painted from the register window anyway.

Changes (renderer only - the bus walk was already correct)

• apply_captured_fetch_geometry accepts comparator-anchored origins
  below the hard start (origin 0 keeps the register view: DDFSTRT=0 is
  the "no window" sentinel; TODO noted).
• effective_ddf_start_hpos / effective_ddf_window keep sub-$18
  starts linear instead of flooring to $18 (values >= $18 unchanged);
  FMODE=0 placement (fetch_origin_native_shift) drops the hard-start
  clamp on its round-up grid alignment (wide-FMODE placement keeps it).
• A row whose register DDFSTRT sits below $18 with no captured fetch
  paints nothing (the no-run rasters of the alternation).
• Lines that begin inside a run carried across the line wrap report no
  run origin (run_origin_cck = None): the continuation tail is not a
  comparator anchor, and those lines keep the register view as before.
• A captured run origin now also rewrites the row's control segments and
  is authoritative for the row's word count, so band-entry rows (copper
  rewrites landing at the start of the next line's segment list) paint
  the captured run instead of a synthetic register-window fallback.

Results (vAmigaTS Agnus/DDF, diff% vs vAmiga 4.4 refs)

Target cases:

The same model closes most of the neighbouring band residuals:
hwstop3_ocs 6.29 -> 0.45, hwstop4/5_ocs 6.42 -> 0.42, hwstop6_ocs
3.72 -> 0.69, hwstop2_ecs 11.14 -> 8.86, hwstop4/5_ecs 10.08 -> 8.64,
hwstop6_ecs 9.94 -> 8.16, single4_ecs 4.92 -> 0.99, single4_ocs
3.12 -> 0.59, single5_ecs 4.06 -> 2.23, single5_ocs 2.41 -> 0.53,
single1/2_ecs -1.6/-1.8, doublematch1_ocs 1.03 -> 0.01, oldhwstop1_ecs
1.44 -> 0.65, oldhwstop2_ecs 7.38 -> 6.77, plus small improvements
across the DDFTIM family. No case in the bucket regressed by more than
0.12pp (reenable1_ecs 0.16 -> 0.28 is the only positive delta).

Ground truth: the oldhwstop3/4 A500 OCS photos shipped with the test
suite, which vAmiga matches.

Gates

• cargo test --lib (1329 green), cargo clippy and cargo fmt --check
  clean.
• 14-demo byte-identity vs merge-base (eon, SOTA, ITM, HAMazing, Gen-X,
  KS1.3/A1200 boots, Second Nature, Roots ECS/AGA, Gods, Rebirth, Turbo
  Tomato, Zool): all IDENTICAL.
• New hardware-behaviour regression tests: sequencer SHW-latch
  alternation and raw-grid anchoring (OCS + ECS), bus-level run-origin
  reporting (carried wrap vs armed line), renderer placement linearity
  below the hard start.